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? semiconductor components industries, llc, 2009 september, 2009 ? rev. 8 1 publication order number: mc14016b/d mc14016b quad analog switch/ quad multiplexer the mc14016b quad bilateral switch is constructed with mos p ? channel and n ? channel enhancement mode devices in a single monolithic structure. each mc14016b consists of four independent switches capable of controlling either digital or analog signals. the quad bilateral switch is used in signal gating, chopper, modulator, demodulator and cmos logic implementation. features ? diode protection on all inputs ? supply voltage range = 3.0 vdc to 18 vdc ? linearized transfer characteristics ? low noise ? 12 nv/ cycle , f 1.0 khz typical ? pin ? for ? pin replacements for cd4016b, cd4066b (note improved transfer characteristic design causes more parasitic coupling capacitance than cd4016) ? for lower r on , use the hc4016 high ? speed cmos device or the mc14066b ? this device has inputs and outputs which do not have esd protection. antistatic precautions must be taken. ? these are pb ? free devices maximum ratings (voltages referenced to v ss ) symbol parameter value unit v dd dc supply voltage range ? 0.5 to +18.0 v v in , v out input or output voltage range (dc or transient) ? 0.5 to v dd + 0.5 v i in input current (dc or transient) per control pin 10 ma i sw switch through current 25 ma p d power dissipation, per package (note 1) 500 mw t a ambient temperature range ? 55 to +125 c t stg storage temperature range ? 65 to +150 c t l lead temperature (8 ? second soldering) 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. temperature derating: plastic ?p and d/dw? packages: ? 7.0 mw/ c from 65 c to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high ? impedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. http://onsemi.com marking diagrams 1 14 pdip ? 14 p suffix case 646 mc14016bcp awlyywwg soic ? 14 d suffix case 751a 1 14 14016bg awlyww a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g = pb ? free indicator soeiaj ? 14 f suffix case 965 1 14 mc14016b alywg see detailed ordering and shipping information in the package dimensions sec tion on page 2 of this data sheet. ordering information
mc14016b http://onsemi.com 2 block diagram control 1 in 1 control 2 in 2 control 3 in 3 control 4 in 4 out 1 out 2 out 3 out 4 13 1 5 4 6 8 12 11 2 3 9 10 v dd = pin 14 v ss = pin 7 control switch 0 = v ss off 1 = v dd on pin assignment 11 12 13 14 8 9 10 5 4 3 2 1 7 6 out 4 in 4 control 4 control 1 v dd in 3 out 3 in 2 out 2 out 1 in 1 v ss control 3 control 2 logic diagram (1/4 of device shown) control out in logic diagram restrictions v ss v in v dd v ss v out v dd ordering information device package shipping ? mc14016bcpg pdip ? 14 (pb ? free) 25 / tape & ammo box mc14016bdg soic ? 14 (pb ? free) 55 units / rail MC14016BDR2G soic ? 14 (pb ? free) 2500 / tape & reel mc14016bfelg soeiaj ? 14 (pb ? free) 2000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
mc14016b http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? (voltages referenced to v ss ) ??????????? ??????????? ??????????? characteristic ??? ??? ??? ???? ???? ???? ??? ??? ??? ???? ???? ? 55 c ???????? ???????? c ???? ???? c ??? ??? ??? ?? ?? ??? ??? ??? ??? ???? ???? ??? ??? ?? ?? ??? ??? ??????????? ??????????? ??????????? ??????????? ??????????? input voltage control input ??? ??? ??? ??? ??? ???? ???? ???? ??? ??? ??? ?? ?? ?? ? ? ? ??? ??? ??? ??? ??? ??? ???? ???? ???? 1.5 1.5 1.5 ??? ??? ??? ?? ?? ?? ? ? ? ??? ??? ??? ??? ??? ??? vdc ???? ???? ???? ??? ??? ??? ?? ?? ?? ? ? ? ??? ??? ??? ??? ??? ??? 3.0 8.0 13 ???? ???? ???? ??? ??? ??? ? ? ? ?? ?? ?? ??? ??? ??? ??? ??? ??? vdc ??????????? ??????????? ??? ??? ? ???? ???? i in ??? ??? ?? ?? ? ??? ??? 0.1 ??? ??? ? ???? ???? 0.00001 ??? ??? 0.1 ?? ?? ? ??? ??? 1.0 ??? ??? adc ??????????? ??????????? ??????????? ??????????? ??????????? ??? ??? ??? ??? ??? ? ???? ???? ???? ???? ???? c in ??? ??? ??? ??? ??? ? ? ? ? ?? ?? ?? ?? ?? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ???? ???? ???? ???? ???? 5.0 5.0 5.0 0.2 ??? ??? ??? ??? ??? ? ? ? ? ?? ?? ?? ?? ?? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? pf ??????????? ??????????? ??????????? ??? ??? ??? ???? ???? ???? ??? ??? ??? ?? ?? ?? ? ? ? ??? ??? ??? 0.25 0.5 1.0 ??? ??? ??? ? ? ? ???? ???? ???? 0.0005 0.0010 0.0015 ??? ??? ??? ?? ?? ?? ? ? ? ??? ??? ??? 7.5 15 30 ??? ??? ??? adc ??????????? ??????????? ??????????? ) ??? ??? ??? ???? ???? ???? ??? ??? ??? ?? ?? ?? ??? ??? ??? ??? ??? ??? ???? ???? ???? ??? ??? ??? ?? ?? ?? ??? ??? ??? ??? ??? ??? ??????????? ??????????? ??????????? ??? ??? ??? ???? ???? ???? ??? ??? ??? ?? ?? ?? ? ? ? ??? ??? ??? 600 600 600 ??? ??? ??? ? ? ? ???? ???? ???? 260 310 310 ??? ??? ??? ?? ?? ?? ? ? ? ??? ??? ??? 840 840 840 ??? ??? ??? ??????????? ??????????? ??????????? ??? ??? ??? ???? ???? ???? ??? ??? ??? ?? ?? ?? ? ? ? ??? ??? ??? 360 360 360 ??? ??? ??? ? ? ? ???? ???? ???? 260 260 300 ??? ??? ??? ?? ?? ?? ? ? ? ??? ??? ??? 520 520 520 ??? ??? ??? ??????????? ??????????? ??????????? ??????????? ??????????? ??????????? ?on? resistance between any 2 circuits in a common package (v c = v dd ) (v in = + 5.0 vdc, v ss = ? 5.0 vdc) (v in = + 7.5 vdc, v ss = ? 7.5 vdc) ??? ??? ??? ??? ??? ??? ? ???? ???? ???? ???? ???? ???? r on ??? ??? ??? ??? ??? ??? ?? ?? ?? ?? ?? ?? ? ? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ???? ???? ???? ???? ???? ???? 15 10 ??? ??? ??? ??? ??? ??? ? ? ?? ?? ?? ?? ?? ?? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ohms ??????????? ??????????? ??????????? ??????????? ? 7.5 vdc) (v in = ? 7.5, v out = + 7.5 vdc) ??? ??? ??? ??? ? ???? ???? ???? ???? ??? ??? ??? ??? 7.5 7.5 ?? ?? ?? ?? ? ? ??? ??? ??? ??? 0.1 0.1 ??? ??? ??? ??? ? ? ???? ???? ???? ???? 0.0015 0.0015 ??? ??? ??? ??? 0.1 0.1 ?? ?? ?? ?? ? ? ??? ??? ??? ??? 1.0 1.0 ??? ??? ??? ??? adc note: all unused inputs must be returned to v dd or v ss as appropriate for the circuit application. 2. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance. 3. for voltage drops across the switch ( v switch ) > 600 mv ( > 300 mv at high temperature), excessive v dd current may be drawn; i.e., the current out of the switch may contain both v dd and switch input components. the reliability of the device will be unaffected unless the maximum ratings are exceeded. (see first page of this data sheet.) reference figure 14.
mc14016b http://onsemi.com 4 ????????????????????????????????? ????????????????????????????????? (c l = 50 pf, t a = 25 c) ???????????????? ???????????????? ???????????????? characteristic ??? ??? ??? ??? ??? ??? ???? ???? ???? ??? ??? ??? ???? ???? ???? ??? ??? ??? ???? ???? ???? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? propagation delay time (v ss = 0 vdc) v in to v out (v c = v dd , r l = 10 k ) control to output (v in 10 vdc, r l = 10 k ) ??? ??? ??? ??? ??? ??? ???? ???? ???? ??? ??? ??? ? ? ? ???? ???? ???? 15 7.0 6.0 ??? ??? ??? ???? ???? ???? ??? ??? ??? ??? ??? ??? ??? ??? ???? ???? ???? ???? ??? ??? ??? ??? ? ? ? ???? ???? ???? ???? 34 20 15 ??? ??? ??? ??? ???? ???? ???? ???? ???????????????? ???????????????? ???????????????? , r out = 10 k , f = 1.0 khz) ??? ??? ??? ??? ??? ??? ? ???? ???? ???? 5.0 10 15 ??? ??? ??? ? ? ? ???? ???? ???? 30 50 100 ??? ??? ??? ? ? ? ???? ???? ???? mv ???????????????? ???????????????? ???????????????? ???????????????? , f = 1.0 mhz, crosstalk 20 log 10 v out1 v out2 ) ??? ??? ??? ??? ? ??? ??? ??? ??? ???? ???? ???? ???? 5.0 ??? ??? ??? ??? ? ???? ???? ???? ???? ? 80 ??? ??? ??? ??? ? ???? ???? ???? ???? db ???????????????? ???????????????? ???????????????? ??? ??? ??? ??? ??? ??? ? ???? ???? ???? 5.0 10 15 ??? ??? ??? ? ? ? ???? ???? ???? 24 25 30 ??? ??? ??? ? ? ? ???? ???? ???? nv/ cycle ???????????????? ???????????????? ???????????????? ??? ??? ??? ??? ??? ??? ???? ???? ???? ??? ??? ??? ? ? ? ???? ???? ???? 12 12 15 ??? ??? ??? ? ? ? ???? ???? ???? ???????????????? ???????????????? ???????????????? ???????????????? second harmonic distortion (v ss = ? 5.0 vdc) (v in = 1.77 vdc, rms centered @ 0.0 vdc, r l = 10 k , f = 1.0 khz) ??? ??? ??? ??? ? ??? ??? ??? ??? ???? ???? ???? ???? 5.0 ??? ??? ??? ??? ? ???? ???? ???? ???? 0.16 ??? ??? ??? ??? ? ???? ???? ???? ???? % ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ? 5.0 vdc, rms centered = 0.0 vdc, f = 1.0 mhz) i loss 20 log 10 v out v in ) (r l = 1.0 k ) (r l = 10 k ) (r l = 100 k ) (r l = 1.0 m ) ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ? ???? ???? ???? ???? ???? ???? 5.0 ??? ??? ??? ??? ??? ??? ? ? ? ? ???? ???? ???? ???? ???? ???? 2.3 0.2 0.1 0.05 ??? ??? ??? ??? ??? ??? ? ? ? ? ???? ???? ???? ???? ???? ???? db ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ? 3.0 db) (v c = v dd , v in = 1.77 vdc, v ss = ? 5.0 vdc, rms centered @ 0.0 vdc) (r l = 1.0 k ) (r l = 10 k ) (r l = 100 k ) (r l = 1.0 m ) ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ???? ???? ???? ???? ???? ???? ??? ??? ??? ??? ??? ??? ? ? ? ? ???? ???? ???? ???? ???? ???? 54 40 38 37 ??? ??? ??? ??? ??? ??? ? ? ? ? ???? ???? ???? ???? ???? ???? mhz ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ???????????????? ? 5.0 vdc) v out v in ?50 db) (r l = 1.0 k ) (r l = 10 k ) (r l = 100 k ) (r l = 1.0 m ) (v c = v ss , 20 log 10 ??? ??? ??? ??? ??? ??? ? ??? ??? ??? ??? ??? ??? ???? ???? ???? ???? ???? ???? 5.0 ??? ??? ??? ??? ??? ??? ? ? ? ? ???? ???? ???? ???? ???? ???? 1250 140 18 2.0 ??? ??? ??? ??? ??? ??? ? ? ? ? ???? ???? ???? ???? ???? ???? khz 4. the formulas given are for typical characteristics only at 25 c. 5. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance.
mc14016b http://onsemi.com 5 figure 1. input voltage test circuit v c v in v out i s v il : v c is raised from v ss until v c = v il . v il : at v c = v il : i s = 10 a with v in = v ss , v out = v dd or v in = v dd , v out = v ss . v ih : when v c = v ih to v dd , the switch is on and the r on specifications are met. figure 2. quiescent power dissipation test circuit figure 3. typical power dissipation per circuit (1/4 of device shown) pulse generator v dd 10 k i d v dd v out v ss v in f c to all 4 circuits p d = v dd x i d 50m 10m 1.0m 100k 10k 5.0k 10,000 1000 100 10 1.0 t a = 25 c 10 vdc 5.0 vdc f c , frequency (hz) , power dissipation ( p d w) control input v dd = 15 vdc typical r on versus input voltage figure 4. v ss = 0 v , on resistance (ohms) r on 700 600 500 400 300 200 100 0 0 2.0 6.0 10 14 18 20 v in , input voltage (vdc) v ss = 0 vdc r l = 10 k t a = 25 c v c = v dd = 10 vdc v c = v dd = 15 vdc
mc14016b http://onsemi.com 6 figure 5. r on characteristics test circuit figure 6. propagation delay test circuit and waveforms v c v in v out r l v out v in r l c l 20 ns 20 ns v dd v ss v in v out t plh t phl 50% 10% 50% 90% figure 7. turn ? on delay time test circuit and waveforms figure 8. crosstalk test circuit v c v out v in r l c l v x 20 ns v c v out v out 10% 90% 10% 90% 90% 50% 10% t pzh t phz v dd v ss t plz t pzl v in = v dd v x = v ss v in = v ss v x = v dd v c v out v in 1 k 10 k 15 pf figure 9. noise voltage test circuit figure 10. typical noise characteristics v c = v dd out in quan-tech model 2283 or equiv 100 k 10 k 1.0k 100 10 35 30 25 20 0 10 vdc 5.0 vdc f, frequency (hz) noise voltage (nv/ cycle) 15 10 5.0 v dd = 15 vdc
mc14016b http://onsemi.com 7 figure 11. typical insertion loss/bandwidth characteristics figure 12. frequency response test circuit v c v out r l v in + 2.5 vdc 0.0 vdc - 2.5 vdc 100 m 10 m 1.0m 100 k 10 k 2.0 0 - 2.0 r l = 1 m and 100 k f in , input frequency (hz) - 4.0 - 6.0 - 8.0 -10 -12 typical inser tion loss (db) 10 k 1.0 k - 3.0 db (r l = 1.0 m ) - 3.0 db (r l = 10 k ) - 3.0 db (r l = 1.0 k ) figure 13. v across switch control section of ic source v load on switch
mc14016b http://onsemi.com 8 applications information figure a illustrates use of the analog switch. the 0 ? to ? 5 v digital control signal is used to directly control a 5 v p ? p analog signal. the digital control logic levels are determined by v dd and v ss . the v dd voltage is the logic high voltage; the v ss voltage is logic low. for the example, v dd = +5 v logic high at the control inputs; v ss = gnd = 0 v logic low. the maximum analog signal level is determined by v dd and v ss . the analog voltage must not swing higher than v dd or lower than v ss . the example shows a 5 v p ? p signal which allows no margin at either peak. if voltage transients above v dd and/or below v ss are anticipated on the analog channels, external diodes (d x ) are recommended as shown in figure b. these diodes should be small signal types able to absorb the maximum anticipated current surges during clipping. the absolute maximum potential difference between v dd and v ss is 18.0 v. most parameters are specified up to 15 v which is the recommended maximum difference between v dd and v ss . figure a. application example +5 v v dd v ss switch in switch out 5 v p-p analog signal 0-to-5 v digital control signals +5 v external cmos digital circuitry 5 v p-p analog signal mc14016b + 5.0 v + 2.5 v gnd figure b. external germanium or schottky clipping diodes v dd v dd d x d x d x d x v ss v ss switch in switch out
mc14016b http://onsemi.com 9 package dimensions pdip ? 14 case 646 ? 06 issue p 17 14 8 b a dim min max min max millimeters inches a 0.715 0.770 18.16 19.56 b 0.240 0.260 6.10 6.60 c 0.145 0.185 3.69 4.69 d 0.015 0.021 0.38 0.53 f 0.040 0.070 1.02 1.78 g 0.100 bsc 2.54 bsc h 0.052 0.095 1.32 2.41 j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l m ??? 10 ??? 10 n 0.015 0.039 0.38 1.01 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. f hg d k c seating plane n ? t ? 14 pl m 0.13 (0.005) l m j 0.290 0.310 7.37 7.87
mc14016b http://onsemi.com 10 package dimensions soic ? 14 case 751a ? 03 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. ? a ? ? b ? g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t ? t ? f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019 7.04 14x 0.58 14x 1.52 1.27 dimensions: millimeters 1 pitch soldering footprint* 7x *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc14016b http://onsemi.com 11 package dimensions soeiaj ? 14 case 965 ? 01 issue b h e a 1 l e q 1 0.13 (0.005) m 0.10 (0.004) d z e 1 14 8 7 e a b view p c l detail p m dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.10 0.20 0.004 0.008 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 1.42 --- 0.056 a 1 h e q 1 l e 10 0 10 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). a b c d e e l m z on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 mc14016b/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative

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